Efficient light coupling between an optical fiber and a silicon waveguide is highly desired for silicon based photonic device and circuit applications. Due to the high refractive index contrast of silicon waveguide systems, obtaining good fiber-silicon waveguide coupling is very challenging particularly for small silicon rib waveguides.
Often is the case that an optical device includes a fiber or waveguide that is intended to be coupled to another waveguide having a significantly larger/smaller cross-sectional size. For example, a planar lightwave circuit (PLC) can have a waveguide on the order of four microns in height to be coupled to an optical fiber with a diameter of about ten microns. One way to couple a port of a relatively large waveguide to a port of a significantly smaller waveguide is by forming a tapered waveguide structure to couple the two waveguides.
U.S. Pat. No. 7,088,890, commonly assigned to Intel Corporation, shows a tapered rib waveguide. As shown in FIG. 1, a waveguide 100 may be formed on a silicon-on-insulator (SOI) substrate comprising an insulation layer 102 and a silicon layer 104. The waveguide 100 generally comprises a tapered section 106 and a final waveguide or rib section 108, shown divided by illustrative line 111. The tapered section 106 comprises a lower taper 110 and an upper, generally wedge shaped taper 112. The upper taper 112 and lower taper 110 include an input facet 114 which may be integrally formed. The lower taper 110 gradually tapers down over length “L” to match the size of an output waveguide 116 in section 108. The upper taper 112 may taper to a point 118 to be generally wedge shaped. This type of waveguide taper 100 may be used to provide high coupling efficiency (coupling loss <1 dB/facet) between a standard fiber (with a modal diameter of ˜9 μm) coupled at the input facet 114 and silicon waveguide 116 with a width or height of ˜4-5 μm.
As above, the taper may be fabricated by etching a silicon-on-insulator substrate with a thick epitaxial layer. This may result in a large difference between the taper height and final photonic waveguide height. Such a topology on the silicon wafer may make it harder to fabricate photonic components together with silicon taper.